Quantifying The Impact Of Series Inductance On E-Load Edge Rates And Current Monitoring Accuracy
by Viktor Vogman, Olympia, Wash., How2Power Today, Apr 15 2024
Focus:
Modern AI processor chips, CPUs, and FPGAs can now draw peak currents over 400 A with
greater than 100-A transients at slew rates exceeding 1000 A/µs. Given these requirements,
there are different obstacles when using conventional test instruments to perform
transient testing on the voltage regulators (VRs). Depending on your requirements, you may
choose to use an off-the-shelf e-load to test your VR, or build your own e-load. In either
case, it is advisable to quantify the impact of the parasitic series inductance in the
current path on the current edge and determine the acceptable value of this inductance
that provides the required e-load performance. This article explains how to do that. It
begins with the selection of a model for an e-load forming the current edges.
What you’ll learn:
- How to determine the maximum acceptable parasitic inductance for transient testing of voltage regulators with e-loads
- How to measure the inductance of the e-load resistor and its current path by measuring the frequency response with commonly available lab instruments
- How to determine the current step sizes an e-load can produce at a given slew rate.
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