Options For Optimizing PFC Efficiency Over Wide Load And Line Ranges
by Joel Turchi, ON Semiconductor, Toulouse, France, How2Power Today, Dec 18 2018
Focus:
The design of power factor correction (PFC) stages for ac-dc power supplies has been discussed
extensively in the literature with many papers and articles discussing techniques for
optimizing PFC efficiency. This 22-page article presents a detailed overview of existing—but
not necessarily well known techniques—for optimizing PFC stage efficiency. The main novelty
here is that these control techniques and architectures are discussed from the viewpoint of
optimizing the average efficiency over wide line and load ranges encountered in actual power
supply applications. After a review of PFC basics, the article identifies the factors that
degrade PFC efficiency. The article then discusses the use of multiple control modes to
maximize efficiency over line and load. The pros and cons of continuous conduction mode,
discontinuous conduction mode, critical conduction mode, and frequency-clamped critical
conduction mode are explained. It then describes and compares different PFC architectures with
a focus on the two-boost bridgeless and interleaved approaches. Respective merits of these
solutions are compared in a 300-W, wide-input-voltage application.
What you’ll learn:
- How to optimize the efficiency of PFC stages over line and load
- How to understand the efficiency pros and cons of DCM, CrM and frequency clamped CrM operating modes in PFC stages
- How to understand the efficiency pros and cons of the boost bridgeless and interleaved PFC architectures
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