Raising The Plateau Level In Valley-Fill PFC Circuits Improves Efficiency
by Viktor Vogman, Power Conversion Consulting, Olympia, Wash., How2Power Today, May 15 2021
Focus:
To meet the IEC 61000-3-2 EMC standard’s limits on harmonic currents, passive power factor
correction (PFC) is typically applied in class C and D equipment. The passive capacitive
PFC circuit, which employs capacitor-diode networks in the valley-fill (VF) PFC
configuration, can improve power factor and reduce harmonic distortion of the input line
current with a reduction in volume versus active PFC. However, operation of the
conventional VF-PFC circuit causes excessive supply voltage variations resulting in higher
current magnitudes and higher power dissipation in the power conversion stages that follow
the PFC stage. After reviewing the operation, characteristics and benefits of conventional
VF-PFC circuits, in which the plateau level is typically one half of the peak ac voltage
or less, this article discusses the efficiency improvement made possible by a novel
implementation in which a higher plateau level is employed. An analysis of power losses in
the dc-dc converter that follows the VF-PFC reveals which higher plateau levels are
optimum in practice.
What you’ll learn:
- How to improve the efficiency of a power supply employing a valley-fill (VF) PFC stage by raising the plateau level
- How to implement plateau levels greater than ½ peak ac voltage in valley-fill rectifiers
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