CMOS Buffers Support Cold Sparing For Space ICs Without The Usual Power Penalty
by Mark Hamlyn, Kyle Schulmeyer, Anton Quiroz and Abhijeet Ghoshal, Apogee Semiconductor, Plano, Texas, How2Power Today, Feb 15 2024
Focus:
In satellites, back-up systems are powered-off or “cold spared” when not in use. Cold-
spare components are electrically isolated from the primary system in operation via
separate power supplies. However, ESD clamping diodes in standard CMOS input and output
buffers cause unwanted current conduction via the cold-sparing power supply, wasting
power. System designers may add isolation circuitry but that increases system complexity.
With these challenges in mind, Apogee Semiconductor has developed proprietary I/O
structures that enable cold-sparing without the power penalty of COTS-based CMOS ICs. In
this article, the authors explain the source of parasitic power consumption and potential
fault conditions in cold-sparing circuits, the limitations of existing solutions, and I/O
structures offered in Apogee’s rad-hard ICs that overcome these problems.
What you’ll learn:
- How to achieve cold sparing in digital logic circuits without the parasitic power consumption usually caused by ESD clamping diodes
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