Video: PDN Basics For Power Designers (Part 2): Keep Impedance Flat

by Steve Sandler, Picotest, Phoeniz, Ariz., How2Power Today, Sep 15 2014

Focus:
In this 6-min. segment, Steve discusses power converter output impedance and why designers of board-level power converters need to keep their output impedance curves flat. The tendency of PDN elements to create resonances or peaks in the PDN impedance vs. frequency curve leads to noise, hence the imperative to minimize the Q of the resonances and keep PDN impedance—and POL or VRM output impedance--flat. The concept of target impedance is discussed. Then, example measurements of POL output impedance are presented, revealing how the impedance curves vary in the on and off states, and how the flatness of the curves can vary for different POL circuits. Then measurements of clock jitter are shown to demonstrate how peaks in PDN impedance induce noise in the clock signal.

What you’ll learn:

• How to understand the impact of POL or VRM output impedance on system noise
• How to understand the relevance of target impedance to power converter design

View this Source (requires a PDF Viewer installed on your device)

• Return to Search Result
• Start Another Search
• How2Power Home
• How2Power Full Website