Interface Panel Addresses Special Connection Challenges In On-Wafer Testing Of Power Semiconductor Devices
by Jennifer Cheney, Keithley Instruments, Cleveland, Ohio , How2Power Today, Mar 13 2015
Focus:
Measuring dc and capacitance parameters for high-power semiconductor devices requires substantial expertise to optimize the accuracy of various measurements. Even for those with this level of expertise, managing set-up changes between on-state current-versus-voltage (I-V), off-state I-V and capacitance-versus-voltage (C-V) measurements can be time consuming and prone to errors; this is especially true in the on-wafer environment. This article begins by examining the various measurement requirements that make wafer-level testing of power devices challenging with respect to making the test set-ups. It then describes the unique features of the Model 8020 interface panel that can be used to simplify the test setups, while making them more accurate and repeatable.
What you’ll learn:
- How to understand the requirements for making wafer-level measurements of power semiconductor devices
- How to simplify test setups for performing capacitance-versus-voltage (C-V) and other wafer-level measurements on power semiconductor devices
- How to improve accuracy and repeatability of wafer-level measurements on power semiconductor devices
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