by Sanjay Havanur and Philip Zuk, Vishay Siliconix, Santa Clara, Calif. , How2Power Today, Apr 15 2015
Focus:
As key contributors of loss in power supply designs, power MOSFETs should be chosen carefully to yield the lowest loss for the given operating environment. But given the wide range of MOSFETs available today, it is not practical to experimentally evaluate all the devices in what would be considered a representative sample. Some designers choose the lowest RDSON device from a given set, which leads to a costly, suboptimal solution. Others rely on the popular figures of merit (FOMs), which are rooted in device design but are “blind†to the application. Instead of applying these generic formulas, designers need to do a simplified loss analysis at the system level and use it as the basis for device selection. This article illustrates the process for the common power factor correction (PFC) stage. However, the principle of loss-derived FOM is applicable to any topology. In the example analysis, a simplified loss equation is derived for a MOSFET in a PFC boost converter operating in continuous conduction mode. The analysis covers power levels from 100 W, which is typical for ac-dc adaptors for notebook computers, up to 500 W, which is the typical rating for desktop silver box power supplies. Using the simplified loss equation, the authors graph power loss versus RDS(ON) for different PFC stage power levels, demonstrating that lowest RDS(ON) does not produce lowest loss.
What you’ll learn:
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